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MPC96877 rev 2, 1/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. this document contains certain information on a new product. specifications and information herein are subject to change without notice. product preview 1.8 v pll 1:10 differential sdram clock driver recommended applications ? ddr ii memory modules ? zero delay board fan-out features ? 1.8 v phase lock loop clock driver for (ddr ii) applications ? spread spectrum clock compatible ? operating frequency: 10 mhz to 500 mhz ? supports ddr2 400/533 mhz and ddr2 667/800 mhz clock data rates ? 1 to 10 differential clock distribution (sstl_18) ? 52-ball vf-bga (fp-mapbga 0.65 -mm pitch) and 40-pin mlf (qfn) ? 52-lead pb-free package available ? external feedback pins (fbin, fbin ) are used to synchronize the outputs to the input clocks ? single-ended input and single-ended output modes ? meets or exceeds jesd82-8 pll standard for pc2-3200/4300 ? auto power down detect logic switching characteristics ? cycle-to-cycle jitter (>165 mhz): 40 ps max. ? output-to-output skew: 40 ps max. functional description the MPC96877 is a high-performance, low- jitter, low-skew, zero-delay buffer that distributes a differentia l clock input pair (ck, ck ) to ten differential pairs of clock outputs (yn, yn ) and to one differential pair of feedback clock outputs (fbout, fbout ). the clock outputs are controll ed by the input clocks (ck, ck ), the feedback clocks (fbin, fbin ), the lvcmos control pins (oe, os), and the analog power input (av dd ). when oe is low, the clock outputs, except fbout/ fbout , are disabled while the internal pll continues to maintain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v dd . when os is high, oe functions as previously described. when os and oe are both low, oe has no affect on y7/y7 , they are free running. when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock inputs (ck, ck ) are logic low, the device enters in a low power mode. an input logic det ection circuit on the differential inputs, independent from input buffers, detects the logic low le vel and performs in a low power state where all outputs, the fe ed- back, and the pll are off. when the clock inputs transition from being logic low to being differential signals, the pll turns b ack on, the inputs and the outputs are enabled, and the pll obtai ns phase lock between the feedback clock pair (fbin, fbin ) and the clock input pair (ck, ck ) within the specified stabilization time. the MPC96877 is able to track spread spectrum clocki ng (ssc) for reduced emi. this device operates from 0 c to 70c. MPC96877 vk suffix 52-ball fp-mapbga package case 1544-01 ddr ii memory clock / zero delay buffer ep suffix 40-pin mlf/qfn package case 1545-01 available ordering options t a 52-ball bga 40-pin qfn 0 c to 70 c MPC96877vk (pb-free) MPC96877ep (pb-free)
advanced clock drivers devices 2 freescale semiconductor MPC96877 figure 1. MPC96877 logic diagram y1 y1 y0 y0 y3 y3 y2 y2 y5 y5 y4 y4 y7 y7 y6 y6 y9 y9 y8 y8 fbout fbout ld * pll ld* or oe ld*, os or oe pll bypass oe os av dd ck ck 10 k?100 k ? gnd fbin fbin * the logic detect (ld) powers down the device when a logic low is applied to both ck and ck . powerdown control and test logic
advanced clock drivers devices freescale semiconductor 3 MPC96877 123456 a b c d e f g h j k nb nb nb nb nb nb nb nb y1 y0 gnd y0 gnd y5 y5 y6 y6 gnd y7 y7 gnd os v ddq fbin v ddq fbin oe fbout v ddq v ddq fbout gnd y8 gnd y1 gnd y2 y2 gnd v ddq v ddq ck v ddq ck v ddq agnd v ddq v ddq av dd gnd y3 gnd y3 y4 gnd y4 gnd y9 y9 y8 ep package (top view) 40-pin te-qfn(6.0 x 6.0 mm body size, 0.5 mm pitch, m0#220, variation vjjd-2, e2 = d2 = 2.9 mm 0.15 mm) package pinouts 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 gnd y1 y1 y0 y0 v ddq y5 y5 y6 y6 v ddq y3 y3 y4 y4 v ddq y9 y9 y8 y8 v ddq v ddq y2 y2 ck ck v ddq agnd av dd v ddq gnd y7 y7 v ddq fbin fbin fbout fbout v ddq oe os vf-mapbga (vk) package
advanced clock drivers devices 4 freescale semiconductor MPC96877 table 1. pin configuration pin bga mlf i/o function agnd g1 7 analog ground av dd h1 8 analog power ck e1 4 input clock input with a (1 0k to 100k) pulldown resistor ck e6 5 input complimentary clock input with a (10k to 100k) pulldown resistor fbin f6 27 input feedback clock input fbin 26 input complimentary feedback clock input fbout h6 24 output feedback clock output fbout g6 25 output complimentary feeback clock output oe f5 22 input output enable (asynchronous) os d5 21 input output select (tied to gnd or v dd ) gnd b2, b3, b4, b5, c2,c5,h2,h5, j2, j3, j4, j5 10 ground v ddq d2, d3, d4, e2, e5, f2, g2, g3, g4, g5 1, 6, 9, 15, 20, 23, 28, 31, 36 logic and output power y[0:9] a2, a1, d1, j1, k3, a5, a6, d6, j6, k4 38, 39, 3, 11, 14, 34, 33, 29,19, 16 output clock outputs y[0:9] a3, b1, c1, k1, k2, a4, b6, c6, k6, k5 37, 40, 2, 12, 13, 35, 32, 30, 18, 17 output complimentary clock outputs table 2. function table inputs outputs pll av dd oe os ck ck y y fbout fbout gnd h x l h l h l h bypassed / off gnd h x h l h l h l bypassed / off gnd lhlh l z l z l h bypassed / off gnd l l h l l z (1) y7 active 1. l (z) means the outputs are disabled to a low state meeting the i odl limit in table 5 . l z (1) y7 active h l bypassed / off 1.8 v nominal l h l h l z (1) l z (1) lh on 1.8 v nominal l l h l l z (1) y7 active l z (1) y7 active hl on 1.8 v nominal h x l h l h l h on 1.8 v nominal h x h l h l h l on 1.8 v nominal x x l l l z (1) l z (1) l z (1) l z (1) off x x x h h reserved
advanced clock drivers devices freescale semiconductor 5 MPC96877 table 3. absolute maximum ratings over free-air operating range (1) 1. stresses beyond those listed under ?absol ute maximum ratings? may cause permanent dam age to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating con ditions? is not implied. exposure to absolute- maximum-rated conditions for extended per iods may affect device reliability. parameter value supply voltage range, v ddq or av dd ?0.5 v to 2.5 v input voltage range, v i (2), (3) 2. the input and output voltage ratings may be exceeded if t he input and output clamp-current ratings are observed. 3. this value is limited to 2.5 v maximum. ?0.5 v to v ddq + 0.5 v output voltage range, v o (1), (2) ?0.5 v to v ddq + 0.5 v input clamp current, i ik (v i < 0 or v i > v ddq ) 50 ma output clamp voltage, i ok (v o < 0 or v o > v ddq ) 50 ma continuous output current, io (v o = 0 to v ddq ) 50 ma continuous current through each v ddq or gnd 100 ma storage temperature range, t stg ?65 c to 150 c table 4. recommended operating conditions rating parameter affected pins min nom max unit output supply voltage v ddq 1.7 1.8 1.9 v supply voltage (1) 1. the pll is turned off and bypassed for test purposes when av dd is grounded. during this test mode, v ddq remains within the recommended operating conditions and not timing parameters are guaranteed. av dd v ddq low-level input voltage (2) 2. v id is the magnitude of the difference between the input level on ck and the input level on ck , see figure 12. time delay between oe and clock output for definition. for ck and ck the v ih and v il limits are used to define the dc low and high levels for the logic detect state. v il oe, os, ck, ck 0.35 x v ddq v high-level input voltage (2) v ih oe, os, ck, ck 0.65 x v ddq high-level output current i oh ?9 ma low-level output current i ol 9 ma input differential-pair cross voltage v ix (v ddq /2) ?0.15 (v ddq /2) +0.15 v input voltage level v in ?0.3 v ddq +0.3 input differential-pair voltage (2) (see figure 9. half-period jitter ) v id dc 0.3 v ddq +0.4 ac 0.6 v ddq +0.4 operating free-air temperature 0 70 c
advanced clock drivers devices 6 freescale semiconductor MPC96877 note: 1. total i dd = i ddq + i add = f ck * c pd * v ddq , solving for c pd = (i ddq + i add )/(f ck * v ddq ) where f ck is the input frequency, v ddq is the power supply and c pd is the power dissipation capacitance. table 5. electrical characterist ics over recommended free-air operating temperature range description parameter affected pins test conditions av dd , v ddq min max unit all inputs v ik i i = ?18ma 1.7 v ?1.2 v high output voltage v oh i oh = ?100 a 1.7 to 1.9 v v ddq ?0.2 v i oh = ?9 ma 1.7 v 1.1 low output voltage v ol i ol = 100 a 1.7 to 1.9 v 0.1 v i ol = 9 ma 1.7 v 0.6 output disable current i odl oe = l, v odl = 100 mv 1.7 v 100 a output differential voltage v od 1.7 v 0.5 v input leakage current i i ck, ck v i = v ddq or gnd 1.9 v 250 a oe, os, fbin, fbin v i = v ddq or gnd 1.9 v 10 static supply current i ddq + i add i ddld ck and ck = l 1.9 v 500 a dynamic supply current i ddq + i add, see note 1 for cpd calculation i dd ck and ck = 270 mhz all outputs open 1.9 v 200 ma table 6. timing requirements over recommended free-air operating temperature range timing requirements av dd , v ddq = 1.8 v 0.1 v unit min max operating clock frequency (1), (2) 1. the pll must be able to handle spread spectrum induced skew. 2. operating clock frequency indicates a range ov er which the pll must be able to lock, but in which it is not required to meet the other timing parameters. (used for low speed system debug.) 10 500 mhz application clock frequency (1), (3) 3. application clock frequenc y indicates a range over which the pl l must meet all timing parameters. 160 450 mhz input clock duty cycle 40 60 % stabilization time (4) 4. stabilization time is the time required for the integrated p ll circuit to obtain phase lock of its feedback signal to its ref erence signal after power up. during normal operation, the stabiliz ation time is also the time required fo r the integrated pll circuit to obtain ph ase lock of its feedback signal to its reference signal when ck and ck go to a logic low state, enter the power-down mode and later return to active operation. ck and ck may be left floating after they have been driven low for one co mplete clock cycle. 15 s
advanced clock drivers devices freescale semiconductor 7 MPC96877 notes: 1. there are two different terminations that are used with the following tests. the loadboard in figure 2. ibis model output load is used to measure the input and output differential-pair cross voltage only. the loadboard in figure 3. output load test circuit 1 is used to measure all other tests. for consistency, equal length cables must be used. 2. static phase offset does not include jitter. 3. period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 4. the output slew rate is determined form the ibis model into the load shown in figure 4. output load test circuit 2 . it is measured single ended. 5. to eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input ck, ck and feedback clock input fbin, fbin are recommended to be nearly equal. the 2.5 v/ns slew rate s are shown as a recommended target. compliance with these nom values is not mandatory if it can be adequately demonstr ated that alternative characteristics meet the requirements o f the reg- istered ddr2 dimm application. table 7. switching characteristics over recommended free- air operating temperature range unless otherwise noted (see notes) description parameter diagram av dd, v ddq = 1.8 v 0.1 v unit min nom max oe to any y/y ten see figure 11 8 ns oe to any y/y tdis see figure 11 8 ns cycle-to-cycle period jitter tjit(cc+) see figure 4 0 40 ps tjit(cc?) 0 ?40 ps static phase offset t( ? ) see figure 5 ?50 50 ps dynamic phase offset t( ? )dyn see figure 10 ?50 50 ps output clock skew tsk(o) see figure 6 40 ps period jitter tjit(per) see figure 7 ?40 40 ps half -period jitter tjit(hper) see figure 8 ?75 75 ps output enable slr(i) see figure 3 and figure 9 0.5 v/ns input clock slew rate, measured single ended 1 2.5 4 output clock slew rate, measured single ended slr(o) see figure 3 and figure 9 1.5 2.5 3 v/ns output differential-pair cross voltage v ox see figure 2 (v ddq /2) ? 0.1 (v ddq /2) + 0.1 v ssc modulation frequency 30 33 khz ssc clock input frequency deviation 0.0 ?0.5 pll loop bandwidth (?3db from unity gain) 2.0 mhz
advanced clock drivers devices 8 freescale semiconductor MPC96877 test circuit and switching waveforms figure 2. ibis model output load figure 3. output load test circuit 1 figure 4. output load test circuit 2 cu877 60 ? 60 ? gnd v dd v dd /2 v ck v ck cu877 z=60 ? l=2.97" r=1m ? c=1pf r=1m ? c=1pf z=60 ? l=2.97" gnd gnd v ddq scope gnd cu877 z=60 ? l=2.97" r=1m ? c=10pf r=1m ? c=10pf z=60 ? z=50 ? r=10 ? r=10 ? z=50 ? l=2.97" v ddq /2 note: v tt = gnd v tt -v ddq /2 -v ddq /2 -v ddq /2 scope v tt
advanced clock drivers devices freescale semiconductor 9 MPC96877 test circuit and switching waveforms (continued) figure 6. static phase offset figure 7. output skew figure 5. cycle-to-cycle period jitter yx, fbout yx, fbout t jit (cc) = t cycle n - t cycle n+1 t cycle n+1 t cycle n ck ck (n is a large number of samples) t (?) n t (?) n t (?) = t (?) n+1 n=n n 1 fbin fbin yx yx t sk(0) yx, fbout yx, fbout
advanced clock drivers devices 10 freescale semiconductor MPC96877 test circuit and switching waveforms (continued) figure 8. period jitter figure 9. half-period jitter figure 10. input and output slew rates f 0 yx, fbout yx, fbout 1 f 0 1 yx, fbout yx, fbout t cycle n t cycle n t jit(per) = f 0 yx, fbout yx, fbout 1 2 * f 0 1 t half period n+1 t half period n n = any half cycle t cycle n t jit(hper) = 80% 80% 20% 20% clock inputs and outputs, oe t r(i) , t r(0) v 80% - v 20% slrr (i/o) = t r(i/o) v 80% - v 20% slrf (i/o) = t f(i/o) t f(i) , t f(0)
advanced clock drivers devices freescale semiconductor 11 MPC96877 test circuit and switching waveforms (continued) figure 12. time delay between oe and clock output figure 11. dynamic phase offset ck ck t (?) t (?) t (?) dyn t (?) dyn fbin fbin ssc off ssc on t (?) dyn t (?) dyn ssc off ssc on oe y/y oe 50% v ddq 50% v ddq 50% v ddq 50% v ddq y y t en t dis
advanced clock drivers devices 12 freescale semiconductor MPC96877 recommended filtering for the analog power supply (av dd ) figure 13. av dd filtering notes: 1. place the 2200pf capacitor close to the pll 2. use a wide trace for the pll analog power and ground. connect pll and caps to agnd to agnd trace & connect trace to one gnd via (farthest from pll). 3. recommended bead: fair rite p/n 2506036017y0 or equivalent (0.8 ohm dc max, 600 ohms @ 100 mhz) gnd card via bead 0603 a vdd 1 ohm r1 r1 agnd v ddq 4.7 uf 1206 4.7 uf 1206 4.7 uf 1206 pll
advanced clock drivers devices freescale semiconductor 13 MPC96877 package dimensions vk suffix 52-ball fp-mapbga non-leaded package case 1544-01 issue o 4.5 7 b a c 0.1 a 0.1 a 0.35 0.25 (0.65) 52x ? 6 5 4 3 2 1 a b c d e f g h j k 52x 1 max 0.45 0.35 all around a1 index area a1 index area seating plane 0.1 a 9x 0.65 5x 0.65 0.325 0.325 5 4 3 m ? 0.15 a m ? 0.08 a b c notes: 1. 2. 3. 4. 5. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. maximum solder ball diameter measured parallel to datum a. datum a. the seating plane, is determined by the spherical crowns of the solder balls. parallelism measurement shall exclude any effect of mark on top surface of package. bottom view top view side view
advanced clock drivers devices 14 freescale semiconductor MPC96877 package dimensions (continued) ep suffix 40-pin mlf/qfn package case 1545-01 b 6 6 a 5.75 5.75 12? 0.1 c 2x 0.1 c 2x 0.1 c 2x 0.1 c 2x pin 1 index area 3.05 2.75 3.05 2.75 exposed die attach pad 36x 0.5 40x (0.4) (0.45) backside pin 1 index (r0.2) (0.2) (0.5) 0.25 0.5 0.3 40x (0.25) 0.70 max 0.9 0.8 0.90 0.75 0.05 0.00 0.60 0.24 0.60 0.24 0.30 0.18 40x 0.1 m a cb 0.05 m c m m detail g detail m 21 10 30 1 31 40 20 11 c 0.5 c 6 7 7 7 7 6 7 8 seating plane detail g view rotated 90? cw detail m preferred backside pin 1 index view m-m notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. maximum package warpage is 0.05 mm. maximumallwable burrs is 0.0706 mm in all directions. this dimension applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, this dimension should not be measured in that radius area. coplanarity applies to leads, corner leads and die attach pad. exact shape and size of this feature is optional. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. die thickness allowable is 0.3.05 mm maximum.
advanced clock drivers devices freescale semiconductor 15 MPC96877 notes
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